This invention relates to a packet switching system and, more particularly, to a mass packet switching system for use in transmitting and switching information at an ultra high speed.
Recently, attention has been directed to a high-speed packet switching system for use in converting into packets all types of information, such as voice, data, picture, or the like, and in transmitting and switching the packets at ultra high speed by using a simplified protocol. For such high-speed packet switching, a large scale packet switching system accommodating hundreds of lines or more is realized by connecting many small or medium scale packet switches in a multistage fashion.
Such a large scale packet switching system is, for example, described by Kentaro Hayashi et al in a paper submitted to "1989-nen Densi Tusin Gakkai Kokan Kenkyukai (1989 A Society for the study of Switching in the Institute of Electronics and Electrical Communication Engineers of Japan)" as Paper No. SSE89-173, pages 61-66, under the title of "A Study on Control Algorithm for Large Scale ATM Switch" according to contributors' translation. The packet switching system is composed of a 3-stage switch network or comprises first through third stage switches. The packet switching system has N.sup.2 input ports and N.sup.2 output ports, where N represents a predetermined number which is not less than two. Each of the input ports is supplied with an input packet having a fixed length. Such an input packet may, for example, be an ATM (asynchronous transfer mode) cell. The first stage switch is connected via N.sup.2 time stampers to the input ports and comprises first through N-th distributing switches. The second stage switch is connected to the first stage switch in a cross link connection fashion and comprises first through N-th primary routing switches. The second stage switch is connected to the third stage switch in the cross link connection fashion and comprises first through N-th secondary routing switches. The third stage switch is connected via N.sup.2 packet sequence correctors to the output ports.
Each of the time stampers assigns a time stamp indicative of a time instant to the input packet supplied thereto to produce a time stamped packet. Each of the first through the N-th distributing switches connects input lines thereof with output lines thereof in one-to-one correspondence irrespective of destination indicated by destination addresses of the time stamped packets supplied thereto. Each of the first through the N-th distributing switches produces distributed packets. Each of the first through the N-th primary routing switches carries out a primary routing switching operation on the distributed packets supplied thereto on the basis of the destination addresses included in the respective distributed packets to produce primary routing switched packets. Each of the first through the N-th secondary routing switches carries out a secondary routing switching operation on the primary routing switched packets supplied thereto on the basis of the destination addresses included in the respective primary routing switched packets to produce secondary routing switched packets. Each of the packet sequence corrector corrects sequence of the secondary routing switched packets successively supplied thereto on the basis of the time stamps assigned to the respective secondary routing switched packets to successively produce sequence corrected packets. The sequence corrected packets are produced via the output ports as output packets.
Each packet sequence corrector comprises a packet distributor, a control circuit, packet buffers, a sorter with a surviving function, and a packet line concentrator. The packet distributor distributes the secondary routing switched packets under the control of the control circuit to make the packet buffers which have no packet store the secondary routing switched packets as stored packets. When any packet in the stored packets is continuously stored in the packet buffers for a time duration longer than a predetermined time interval, the packet buffers deliver all of the stored packets to the sorter in response to the buffer control signal supplied from the control circuit. The sorter selects, as a selected packet, one of the stored packets that is assigned with the time stamp indicating the earliest time instant. The sorter delivers a selection control signal to a selected one of the packet buffers that stores the selected packet. Responsive to the selection control signal, the selected packet buffer sends the selected packet to the packet line concentrator. The packet line concentrator delivers the selected packet as the sequence corrected packet to the output port. The predetermined time interval is equal to the difference between the maximum delay time interval and the minimum delay time interval for which the input packet passes through the primary routing switch and the secondary routing switch.
At any rate, the packet sequence corrector carries out a packet sequence correction operation only when a packet is continuously stored in the packet buffers for a time duration longer than the predetermined time interval. Therefore, the packet is placed in the wait state although there is no reversal for sequence of the packets. As a result, the conventional packet switching system is defective in that it has the larger delay time for the packets. In addition, it is necessary for the packet sequence corrector to compare the time stamps assigned to all of the stored packets. Accordingly, the conventional packet switching system is disadvantageous in that it is complex to control.